A significant trend throughout integrated circuit (IC) development is the downsizing of IC components. These integration improvements are two-dimensional (2D) in nature where the ICs are integrated on a surface of a semiconductor wafer. Although dramatic improvement in lithography has enabled greater results in 2D IC formation, there are physical limits to the density that can be achieved in two dimensions. Also, when more devices are put into one chip, more complex design costs are required.
In an attempt to further increase circuit density, three-dimensional (3D) ICs have been developed. For example, two dies are bonded together; and electrical connections are formed between each die. The stacked dies are then bonded to a carrier substrate by using wire bonds and conductive pads. In another example, a chip on (chip on substrate) (Co(CoS)) or (Chip on wafer) on substrate ((CoW)oS) technique is developed.
However, conductive bumps adjacent to edges or corners of an interposer or dies can result in cracking during cooling down or a stressing test. During cooling down of chip joints, conductive bumps disposed between the interposer and the circuit board are subject to shearing and stress, which results from the different thermal expansion due to different thermal coefficients.